Synchronous semiconductor memory device employing temporary data output stop scheme
US6101151A · kind A · utility
58Cited by
3References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 20, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Nov 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a synchronous semiconductor memory device in which an internal clock signal from an internal timing clock signal generating circuit is branched in the form of a tree by driver circuits and applied to output buffers and data are output in synchronization with the internal clock signal, the driver circuit of the first stage is constituted by an NAND gate and an inverter. When output is to be temporarily stopped, an enabling signal is set to "L" level, so that the NAND gate is closed, output of the clock signal to each driver circuit is stopped, and thus power consumption is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.