Counter circuit
US6101233A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Sep 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Counter circuits causing no noise at the time of operation are provided. Three stage of D-type flip-flops (FF1 to FF3) are connected in series. A delay element (11) delays a signal (S2) that is Q output of the flip-flop (FF1) by a delay time (d2) to output a delay signal (S2D), and a delay element (12) delays a signal (S3) that is Q output of the flip-flop (FF2) by a delay time (d3) to output a delay signal (S3D). Here, the relationship among the delay time (d2, d3) and a clock cycle (Tc) is set so as to satisfy the condition of {Tc>d2>d3}. NOR gate for three inputs (G1) receives delay signals (S2D, S3D) and a signal (S4) i.e., Q output of the flip-flop (FF3), and performs NOR operation on these signals (S2D, S3D and S4), thereby outputting a signal (S1) to D input of the flip-flop (FF1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.