System for providing an increase in digital data transmission rate over a parallel bus by converting binary format voltages to encoded analog format currents
US6101561A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Feb 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit, for use with a parallel data bus of defined width, which provide a parallel data transmission and reception rate which is greater than the defined width of the parallel data bus. With respect to improving transmission, provided is a width-reduction circuit element, having at least two inputs through which are received a first set of parallel digital data signals and having one or more outputs through which are transmitted a second set of parallel digital data signals where the second set is both smaller than the first set and representative of the information contained within the first set. The one or more outputs interface with a parallel connector which is sufficient to form an operable connection with the parallel data bus of defined width. With respect to improving reception, provided is a width-expansion circuit element having one or more inputs through which are received a second set of parallel digital data signals and having at least two outputs through which are transmitted a first set of parallel digital data signals where the first set is both larger than the second set and representative of information encoded within the second set. The one or more…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.