Digital signal processor for delayed signal processing using memory shared with another device
US6101583A · kind A · utility
2Cited by
10References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 16, 1996 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Dec 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In each sampling period, sample data and a count value WA of a ring buffer counter 11 are supplied to a RAM 202 through a bus control circuit 14 as write data and a write address. Each cache block stored in a data buffer DB.sub.0 and so on is used for executing an FIR filtering operation. As an amount of unused sample data in the cache block is decreased, subsequent cache blocks used for a subsequent FIR filtering operation are supplemented to the data buffers DB.sub.0 and so on by the cache counter units CC.sub.0 and so on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.