High performance shared cache

US6101589A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Horst Fuhrmann · Bornsteiner Straße, DE
• Jorg Wedeck · Holzgerlingen, DE
• Dieter Wendel · Schenefeld, DE
• Udo Wille · Holzgerlingen, DE

Key dates

• Filing date: Apr 10, 1998
• Grant date: Aug 8, 2000
• Expiry date: Apr 10, 2018

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/0857
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A high performance cache unit in a multiprocessing computer system comprises a shared level n cache 15 which is divided into a number of independently operated cache cores each of which containing a cache array for being used as buffer between plurality of processing units PU0-PU1 and a memory 18. Data requests and response requests issued by the processing units are separately executed in an interleaved mode to achieve a high degree of concurrency. For this purpose each cache core comprises arbitration circuits 101, 106 for an independent selection of pending data requests and response requests for execution. Selected data requests are identified by a cache directory lookup as linefetch-match or linefetch-miss operations and separately stored during their execution in operation registers 112, 114. Selected response requests are stored independently of the data requests in registers 105, 108, 109 and successively executed during free operation cycles which are not used by the execution of data requests. In this manner each of the cache cores can concurrently perform a linefetch-match operation, a linefetch-miss operation and a store operation for one processing unit or for a number…