Architecture providing isochronous access to memory in a system
US6101613A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1998 |
| Grant date | Aug 8, 2000 |
| Priority date | — |
| Expiry date | Dec 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture is provided for isochronous access to memory in a system in which a stream of information may be sent to a memory unit. The stream is divided into a plurality of service periods with a specified maximum amount of information in selected service periods, and selected service periods have a first amount of information associated with asynchronous information and a second amount of information associated with isochronous information. In addition to sending a stream of information, a request for isochronous information from the memory unit may be sent. In this case, a stream of the requested information may be received from a memory unit a predetermined number of service periods after the sending of the request. This stream is also divided into a plurality of service periods with a specified maximum amount of information in selected service periods, and each service period has a first amount of information associated with asynchronous information and a second amount of information associated with isochronous information. In either case, the second amount of information may contain asynchronous information when less than all of the second amount of information is used fo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.