Circuit board features with reduced parasitic capacitance and method therefor
US6103134A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1998 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Dec 31, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0551
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for fabricating circuit board conductors with desirable processing and reduced self and mutual capacitance. The method generally entails forming a metal layer on a positive-acting photodielectric layer formed on a substrate, and then etching the metal layer to form at least two conductor traces that cover two separate regions of the photodielectric layer while exposing a third region of the photodielectric layer between the two regions. The third region of the photodielectric layer is then irradiated and developed using the two traces as a photomask, so that the third region of the photodielectric layer is removed. The two remaining regions of the photodielectric layer masked by the traces remain on the substrate and are separated by an opening formed by the removal of the third dielectric region. As a result, the traces are not only separated by a void immediately therebetween formed when the metal layer was etched, but are also separated by the opening formed in the photodielectric layer by the removal of the third region of the photodielectric layer. Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor winding…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.