Fabricating method of multi-level wiring structure for semiconductor device
US6103617A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 1999 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | May 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabricating method of a multi-level wiring structure for a semiconductor device that improves the resolution of photoresist film pattern by reducing a photoresist film and is capable of fabricating a semiconductor device of a high reliability by using an improved via hole mask includes the steps of sequentially forming a first insulating film, a first etching stop film, a second insulating film and a second etching stop film on a lower conductive layer pattern, forming a trench by etching the second etching stop film, the second insulating film and the first etching stop film which corresponds to an upper conductive layer pattern, forming a photoresist film on an entire upper surface of the resultant semiconductor substrate so that a thin photoresist film at about 1000-3000 .ANG. is formed on the second etching stop film, forming an opening on a predetermined portion of the trench by performing a photolithography, forming a via hole by etching the first insulating film through the opening, and filling a conductive material in the via hole and the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.