Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies
US6104054A · kind A · utility
102Cited by
10References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 1999 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | May 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for reducing the parasitic capacitance and capacitive coupling of nodes (106) in a dielectrically isolated integrated circuit (100) using layout changes. A separate area of floating silicon (110) is created adjacent two or more dielectrically isolated nodes (106). The two or more nodes (106) are chosen that "slew together" (i.e., nodes that are required to change by the same voltage at the same time). The area of floating silicon (110) is created by placing an additional trench (112) around both of the dielectrically isolated nodes (106).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.