Electrically alterable non-volatile semiconductor memory device
US6104057A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1998 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Aug 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically alterable non-volatile memory device is disclosed. In the device architecture of the memory device, control gates are formed, divided corresponding to the blocks and interconnected independently within each block, to further be connected to a metal gate line through block select MOS transistors which are formed on a semiconductor substrate between the blocks. All gate electrodes of the block select MOS transistors which are connected to the control gates interconnected as above within each block are further connected each other. These block select transistors can be controlled by applying erase block signals such as, EBS0, EBS1 and so on, to respective transistors. In addition, the control gates are further connected to a decoder such that some of these control gates may be selected through metal control gate lines. With the block select transistors together with the metal control gate line provided as above, erasing can be achieved in the unit of memory cells which are connected to a metal control gate line within a block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.