Lead frame used for semiconductor chips of different bit configurations
US6104083A · kind A · utility
7Cited by
4References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1997 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Sep 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The lead frame comprises a plurality of inner leads adhered onto a semiconductor chip by means of adhesive tape provided on the semiconductor chip, and a plurality of outer leads each formed integrally with corresponding one of the inner leads. The plurality of inner leads include an inner lead group having a plurality of inner leads each of which is connected to the corresponding one of electrodes of the semiconductor chips, and the other inner lead group having a plurality of inner leads disconnected from the electrodes of the semiconductor chips and cut off from at least one of the outer leads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.