Method and apparatus for data forwarding in a processor having a dual banked register set
US6104731A · kind A · utility
4Cited by
1References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 23, 1997 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Dec 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3826
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit including a multiplexer and a comparator. The multiplexer has one input coupled to a portion of an odd result address bus and another input coupled to a portion of an even result address bus. The control input of the multiplexer is coupled to a least significant bit line of a source address bus. The output of the multiplexer is coupled to one input of the comparator, and the other input is coupled to a portion of the source address bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.