Scatter gather memory system for a hardware accelerated command interpreter engine
US6105075A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 1998 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | May 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware accelerated memory system in a hardware accelerated I/O data processing engine that gathers and maintains pointers to a set of widely distributed source and/or destination data locations. The locations of the source and/or destination data locations operated on by the I/O data processing engine can include a memory local to the command interpreter and a memory remote from but accessible to the command interpreter by way of an I/O bus. Each source and/or destination scatter/gather list contains pointers to actual data locations that are either in a memory local to the command interpreter or a memory remote from the command interpreter but accessible by way of an interconnecting I/O bus. Each data location entry in a scatter/gather list is also accompanied by a byte count indicative of the total number of bytes at a given data location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.