Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems
US6105119A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 1997 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Apr 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (1720) includes a dual-port memory (3330.1) having a first memory port (Port A) and a second memory port (Port B), a bus interface block (5010) including bus master (5016) and bus slave circuitry (5018), and a byte-channeling block (5310) coupled between the first memory port (Port A) and the bus interface block (5010) operable to convert non-aligned data addresses into aligned data. Advantageously, this invention includes a single bus master serving all application hardware. This relieves the host of the extra burden of communicating to slave circuits, reducing host I/O MIPS significantly. The digital signal processor with an ASIC wrapper of this invention together provide super-bus-mastering to access the entire memory space in the system, including the entire virtual memory space accessible by the host processor. Other processes, systems, devices and methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.