Method for implementing multiple format addressing in an embedded microcontroller, a compiler being arranged for implementing the method, and a microcontroller being arranged for using the method and compiler
US6105120A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1997 |
| Grant date | Aug 15, 2000 |
| Priority date | — |
| Expiry date | Sep 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0623
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple format addressing is implemented in a microcontroller that has both ROM and RAM memory facility, processing facility, and bus facility for interconnecting the memory and processing facilities, through using a low address field for local addressing, and at least one facultative high address field for extended addressing. In particular, the high address field is provided in a first addressing format as a segment address, and in a second addressing format as containing a RAM/ROM selection bit. More in particular, the high address field can be provided in a third addressing format as containing a RAM/ROM selection bit and a segment address in respective mutually exclusive fields.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.