Semiconductor device and method of fabricating the same
US6107182A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1998 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Sep 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300.degree. C. to 550.degree. C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100.degree. C.; (e) a step of forming a first aluminum layer comprising one of aluminum and an alloy in which aluminum is the main component on the wetting layer at a temperature of no more than 200.degree. C.; and (f) a step of forming a second aluminum layer comprising one of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.