Isolated multi-chip devices
US6107674A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 1993 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | May 5, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/31681
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device structure in which a power semiconductor device is used as the substrate for the structure. Initially, a first metallization layer is formed on the power semiconductor device. Then, a dielectric passivation layer is formed over the first metallization layer, the dielectric passivation layer having apertures through which the first metallization layer may be accessed. A polymer passivation layer is then formed on the dielectric passivation layer, the polymer passivation layer also having apertures through which the first metallization layer and the dielectric passivation layer may be accessed. A second metallization layer is then formed on the polymer passivation layer to which at least one electronic component is connected. In specific embodiments, the polymer passivation layer includes polyimide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.