Input/output circuit
US6107832A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 1999 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input/output circuit in which, one of the two output signals from a signal level converting circuit is inputted into one input terminal of a NAND gate and into one input terminal of a NOR gate, while the other signal is inputted into the other input terminal of the NOR gate and also to the other input terminal of the NAND gate through an inverter. An output signal from the NAND gate and NOR gate is inputted into the gate of a PMOS transistor and into a gate of a NMOS transistor, which makes it possible to prevent the PMOS transistor and NMOS transistor from concurrently being ON and also prevents a through current from flowing therethrough.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.