Digital phase comparator and frequency synthesizer
US6107890A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1999 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | May 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The phase of a pulsed test signal is measured with reference to a reference signal of constant frequency by sampling the test signal at times determined by transitions in the reference signal and comparing the sampled test signal with the output of a phase accumulator clocked by the reference signal. A resulting measurement signal represents a difference in the number of transitions occurring in the sampled test signal and a reference state signal output by the phase accumulator. The measurement signal may be averaged and integrated to obtain an error signal which may then be filtered to provide a control signal for an oscillator. A digital frequency synthesizer is provided by frequency dividing the output of the oscillator by a constant multiple to obtain the test signal and integrating an offset signal in addition to the averaged measurement signal so that the operating frequency of the oscillator is offset from a nominal frequency by an amount determined by the offset signal. The digital frequency synthesizer is suitable for use in a synchronous equipment timing source within a telecommunications multiplexer operating at a line transmission rate of 155.52 MHz.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.