NFET/PFET RAM precharge circuitry to minimize read sense amp operational range
US6108256A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 1999 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Sep 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a precharge circuit for precharging bit lines coupled to a read sense amplifier and a RAM cell. The precharge circuit includes a set of precharge transistors, a first transistor, and a transistor pair. The set of precharge transistors is coupled to said bit lines for precharging said bit lines with one precharge transistor per bit line. The first transistor is coupled to turn on said set of precharge transistors when said RAM cell is not being read. The first transistor is operative to reduce the gate-to-source voltage V.sub.GS of said set of precharge transistors such that each of said precharge transistors output a reduced precharge voltage to the associated bit line. The transistor pair is coupled to said set of precharge transistors and is operative to switch said precharge transistors for reading said RAM cell. In this configuration, the RAM cell outputs a differential signal onto said bit lines when said precharge transistors are turned off. The read sense amplifier monitors said bit lines to detect said differential signal on said bit lines as a data bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.