Arithmetic logic unit controller for linear PCM scaling and decimation in an audio decoder
US6108622A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1998 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Jun 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/2537
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An audio decoder converts a linear PCM audio data packet into two concurrently provided digital audio sample sequences: a high-quality sequence and a decimated sequence. In one embodiment, the audio decoder is part of an audio system that further includes two audio devices. The first audio device is configured to produce an audio signal from a 96 kHz sequence, and the second audio device expects a 48 kHz sequence. The audio decoder includes an input interface, an arithmetic logic unit (ALU), and two output buffers. The input interface is configured to receive a linear PCM audio data packet and to reconfigure bytes as necessary to reconstruct a sequence of unscaled audio samples. The ALU multiplies each of the unscaled audio samples by a gain factor and buffers the resulting scaled audio sample sequence in a first output buffer. After samples for two sampling instants have been processed, the ALU then retrieves a string of samples from the first output buffer, multiplies them by decimation filter coefficients, and adds the products to form decimation samples for one sampling instant. The decimation samples form a decimated audio sequence which is buffered in the second output buffer…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.