Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration to allow access to a common internal bus
US6108725A · kind A · utility
Inventor
Key dates
| Filing date | Jul 6, 1998 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Jul 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel low cost/high performance multi-port internally cached dynamic random access memory architecture called `AMPIC DRAM`, and consequentially a unique system architecture which eliminates current serious system bandwidth limitations, providing a means to transfer blocks of data internal to the chip, orders of magnitude faster than the traditional approach, and with the chip also interconnecting significantly higher numbers of resources with substantially enhanced performance and at notably lower cost. Through use of a system configuration based on this novel architecture and working equally efficiently for both main memory functions and as graphics memory, thus providing a truly low cost, high performance unified memory architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.