Information processor and method of its component arrangement
US6108731A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 1998 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Aug 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/186
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of processor elements (31 to 34) are disposed on a main board (710) in line in parallel with a first edge of the main substrate (710). Expansion board slots (331 to 336) into which an expansion board for mounting an I/O interface thereon is plugged and a memory connector (341) to which a memory board for mounting a memory thereon is connected are disposed in a region of the main substrate opposite to the first edge. The long sides of the expansion board slots (331 to 336) and the memory board connector (341) are in parallel with the first edge. A bridge LSI for executing protocol conversion between processor buses (210, 211, 212) and an I/O bus (230) and memory controllers (151, 152) for controlling memory access are disposed in regions adjacent to both the expansion board slots and the processor elements. The processor bus (210, 211, 212) is bent into a protuberance shape so that a branch does not substantially form and the bridge LSI and memory controller are substantially at the middle portion of a plurality of processors. The processor bus connects the processor elements, the bridge LSI and the memory controller in this order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.