Technique for performing DMA including arbitration between a chained low priority DMA and high priority DMA occurring between two links in the chained low priority
US6108743A · kind A · utility
48Cited by
5References
14Claims
0Family size
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Key dates
| Filing date | Feb 10, 1998 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Feb 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention, in one embodiment, is a method for performing direct memory access. The method includes arbitrating between a chained, low priority, direct memory access and a high priority, direct memory access, the arbitration occurring between two links in the chained, low priority, direct memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.