Multiple masters in a memory control system
US6108758A · kind A · utility
9Cited by
3References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1997 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Aug 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for multiple masters for a memory control system is provided. The memory control system includes a first master, and a memory coupled to the first master using a memory channel. A second master is coupled between the first master and the memory. The second master writes to and reads from the memory using a transmission reflection from the first master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.