Apparatus and method for hybrid pin control of boundary scan applications
US6108807A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 1997 |
| Grant date | Aug 22, 2000 |
| Priority date | — |
| Expiry date | Jul 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In accordance with the present invention, an apparatus and method for implementing a new user-defined B-S instruction called PINCONTROL is disclosed. When PINCONTROL is in effect, an output pin can be configured to be either driving a constant 0, driving a 1, in the high-impedance (high-Z) state or in the control of system logic; and different pins of the same chips may assume different configurations depending on the content of the capture and update portion of the B-S register. This instruction provides an improved fault insertion capability. For example, if it is desired to inject a stuck-at-0 fault at pin p, pin p can be configured to drive a constant 0 while allowing other pins to function normally. A stuck-at-1 fault can also be injected by configuring pin p to drive a constant 0 while allowing other pins to function normally. An open fault can also be injected by configuring pin p into a high-impedance state. As will described, multiple faults of the same or different type may be injected, as can transient faults with different durations. This kind of fault insertion capability can be used to verify the fault-tolerant capability of a fault-tolerant system and for the verific…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.