Semiconductor integrated circuit and manufacturing method thereof
US6110772A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1998 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Jan 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
A semiconductor IC including a resistance element on a circuit substrate. The resistance element includes a resistance layer formed on an insulating layer. The resistance layer is formed using a Si layer obtained by forming an a-Si layer, doping the a-Si layer with impurities, and heating the doped a-Si layer to diffuse the impurities while substantially preserving the fineness of the a-Si layer surface. Preferably, a SiN layer is provided lying beneath the resistance layer. A capacitor may be integrated on the same circuit substrate where the resistance element is formed. In this case, a lower electrode, a SiN dielectric layer, and an upper electrode are formed in this order to constitute a capacitor. The SiN dielectric layer of the capacitor is formed extending from a capacitor formation region to another region, so that the resistance layer of the resistance element is formed on the extending SiN dielectric layer. The lower and upper electrodes of the capacitor may be formed using an a-Si layer, similar to the resistance layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.