Process for fabricating trench isolation structure for integrated circuits
US6110797A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1999 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Dec 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trench isolation structure featuring a shallow trench overlying a deep trench is fabricated avoiding creation of irregularities on the deep trench sidewalls. Such sidewall irregularities are conventionally associated with interaction between etchant and unexposed positive photoresist formed at the bottom of the deep trench during prior shallow trench photolithography steps. In one embodiment of the present invention, a deep trench is created and then a positive photoresist mask is patterned. The positive photoresist mask is utilized to etch a barrier selective to underlying single crystal silicon in anticipated shallow trench regions. Once the barrier has been removed, the positive photoresist mask is stripped, removing any unexposed positive photoresist remaining within the deep trench. Single crystal silicon revealed by removal of the barrier is etched to create the shallow trench, with remaining barrier material sacrificed to protect the underlying surface against this etching. In an alternative embodiment, a negative photoresist mask is employed during shallow trench photolithography, with development of the negative photoresist effective to remove the photoresist from the de…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.