Trench contact process
US6110799A · kind A · utility
105Cited by
10References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1997 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
A trench process for establishing a contact for a semiconductor device with trenches such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs which reduces the number of masks and eliminates the need for lateral diffusion into the trench channel region. Improved control of the parasitic transistor in the trench MOSFET is also achieved. The cell size/pitch is reduced relative to conventional processes which require source block and P+ masks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.