Method for controlling delays in silicon on insulator circuits
US6111455A · kind A · utility
19Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1998 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Dec 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/163
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for controlling delays in silicon on insulator circuits is disclosed. A semiconductor integrated circuit device comprises a first circuit and a second circuit. The first circuit includes multiple transistors, some of which have a floating body. In addition, the first circuit includes an input and an output. The second circuit is selectively coupled to a floating body of some of the transistors in the first circuit in order to control the delay of the output of the first circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.