Method to improve the jitter of high frequency phase locked loops used in read channels
US6111712A · kind A · utility
110Cited by
27References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1998 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Mar 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system and method is provided to improve the jitter performance of high frequency synthesizers used in read/write channel circuits. The frequency synthesizer is implemented with multiple phase locked loops arranged in a cascaded fashion to increase the update rates at which the cascaded loops operate at for a given frequency resolution of the synthesizer. The cascaded or staged phase locked loops may be utilized for generating read, write, and servo clocks for a read/write channel circuit. The cascaded phase locked loops may also be arranged such that one or more stages are shared to generate the read, write or servo clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.