Method and apparatus for translating signals between clock domains of different frequencies
US6112307A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1995 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Nov 9, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A synchronizing circuit translates signals in a slow clock domain into a fast clock domain. The frequency of the slow clock is a submultiple of the fast clock frequency. A synchronizing pulse signal is developed at the frequency of the slow clock, but is phase synchronized to the fast clock. The synchronizing pulse signal is employed to gate the signal in the slow clock domain so that it is synchronized in the fast clock domain. In a system where the ratio between the fast clock frequency and slow clock frequency is determined by a frequency divisor signal, a snooping circuit is employed to capture the frequency divisor signal to achieve rapid synchronization between the clock domains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.