Processor performance counter for sampling the execution frequency of individual instructions
US6112317A · kind A · utility
56Cited by
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16Claims
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Key dates
| Filing date | Mar 10, 1997 |
| Grant date | Aug 29, 2000 |
| Priority date | — |
| Expiry date | Mar 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes an execution pipeline and a retire unit coupled to an end of the execution pipeline. The processor executes instructions of a program. An apparatus for collecting performance data while the instructions are executing includes a register coupled to the retire unit of the processor. Means are provided for incrementing the register whenever an instruction is retired from the execution pipeline. In addition, the apparatus includes means for generating an interrupt to an interrupt handler whenever the register is incremented to a predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.