Semiconductor packaging method
US6114191A · kind A · utility
19Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Dec 3, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices 340 are formed in semiconductor wafer 300. Contact pads 332 are formed in each die 330. An interconnect connects the contact pads 332 to die surface contact regions 210, 212. Scribe trenches 348 are formed in device wafer 300; corresponding trenches 358 are formed in cover wafer 360. The cover wafer 360 is thinned to open scribe trenches 348. Conductive vias 310-313 connect the contact pads 210, 212 to external surface bump contacts 333.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.