Chip-scale electronic component package
US6114635A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Jul 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H9/1092
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A chip-scale sized package for acoustic wave devices, acoustic resonators and similar acoustic devices located upon, or fabricated upon, or as part of, a die. The package includes a lid that is bonded to the die by a strip of solder or other bonding material so as to leave a space between the lid and that portion of the die that acoustically deforms or vibrates. The upper surface of the lid includes electrical connectors that are electrically connected via plated through holes or other means to electrical connectors, or pads on the lower surface of the lid, which pads, in turn, are electrically connected by solder or other electrically conducting material to electrical connectors to the device that are located upon the surface of the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.