Flash memory cell using poly to poly tunneling for erase

US6114723A · kind A · utility

Assignee

• WINDBOND ELECTRONICS CORP. · TW

Inventor

• Len-Yi Leu · Baoshan, TW

Key dates

• Filing date: Sep 18, 1998
• Grant date: Sep 5, 2000
• Expiry date: Sep 18, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6891

Abstract

An improved split gate flash memory cell is disclosed whose floating gate is formed to have a reentrant angle such that its width increases with increased distance from the substrate so as to minimize the possibility of defects in the poly oxide layer overlaying the floating gate. The split gate flash memory is fabricated using a process comprising the steps of: (a) forming a floating gate with an overlaying poly oxide layer on a substrate, wherein the floating gate is etched to have a reentrant angle such that its width generally increases with a distance from the substrate; (b) forming a CVD nitride spacer on the floating gate using a CVD nitride deposition, then anisotropic etching the CVD nitride to form a nitride spacer adjacent to the floating gate; (c) forming a control gate on the floating gate wherein the control gate and the floating gate are separated by the poly oxide and the nitride spacer; and (d) forming a source and drain in the substrate using a source and drain implantation.