Vertical PNP transistor and relative fabrication method
US6114746A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 26, 1996 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Jul 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/177
Abstract
A vertical PNP transistor integrated in a semiconductor material wafer having an N type substrate and an N type epitaxial layer forming a surface. The transistor has a P type buried collector region astride the substrate and the epitaxial layer; a collector sinker insulating an epitaxial tub from the rest of the wafer; a gain-modulating N type buried base region astride the buried collector region and the epitaxial tub, and forming a base region with the epitaxial tub; and a P type emitter region in the epitaxial tub. An N.sup.+ type base sinker extends from the surface, through the epitaxial tub to the buried base region. The gain of the transistor may be modulated by varying the extension and dope concentration of the buried base region, forming a constant or variable dope concentration profile of the buried base region, providing or not a base sinker, and varying the form and distance of the base sinker from the emitter region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.