Phase detectors
US6114879A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1999 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Jan 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/10009
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase detector determines an error value dependent on the relative phase between a local oscillator signal, used as the system clock, and an input signal received over a PR (a, b, a) channel. The phase error value is used to control a phase locked loop (FIG. 1, not shown). The received signal is sampled at regular intervals dependent on the local oscillator signal. A threshold slicer 22 selects an ideal sample value for a sampling point by comparing the sampled value to three thresholds provided on respective ones of slicer threshold inputs 23, 24 and 25. A subtracter 27 determines a difference value corresponding to a difference between the ideal sample value and the actual sample value for that sampling point. A delay register 28 and a subtracter 29 operate to determine the sense of change to the current ideal sample value from an ideal sample value for a preceding sample point. An output of the subtractor is applied to the switching input of a switch, which thereby provides as an output signal either the difference value or the inverse of the difference value, provided by an inverter 32, dependent on the detected sense of change.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.