(N) bit (M) ternary coding circuit
US6114979A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 21, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Jan 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A coding circuit of the present invention converts n-bit binary data word at a prescribed clock cycle (t) into to an m-trit ternary code word, where n and m are integers and n.gtoreq.m. The coding circuit includes an (x) number of storage elements or latches and a (y) number of coders, each storage element or latch receiving (m.div.x) bits of the binary data word at a clock cycle of (t.div.x). After a prescribed delay period, a corresponding storage element or latch outputs the sampled bits to a corresponding coder at an increasing or decreasing edge of the clock signal. Each coder codes the sampled bits to (m.div.y) ternary code. The each of the coders outputs (m.div.y) ternary code onto a corresponding signal line of a bus. Hence, the coding circuit outputs m-trit ternary code word onto the bus. An exemplary coding circuit is illustrated where n=8, m=6, t=25 MHz, x=2 and y=2, and D flip-flops are used for the storage elements and latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.