Nonvolatile semiconductor memory device using SOI
US6115287A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Nov 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND type EEPROM according to the present invention is formed on an SOI substrate as follows. Silicon thin films (element regions) isolated in a grid pattern are formed on an insulation layer on a silicon substrate. A trench between the silicon thin films is filled with insulating material. Thus, the elements in the row direction are isolated completely by the insulating material. A silicon thin film on which a memory cell is formed, contains a very small amount of n-type impurities and is close to an intrinsic semiconductor. A silicon thin film on which a select gate transistor is formed is of a p-type. The source and drain diffusion layers of the memory cell and select gate transistor are of an n-type. The channel of each of memory cells constituting a NAND string is constituted of at least two regions having different threshold voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.