Semiconductor memory device capable of reducing a leak current flowing through a substrate
US6115296A · kind A · utility
10Cited by
3References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 11, 1999 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Jan 11, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device composed of a set of SRAM cells connected in common to one another through a word line and a common connection line, a substrate potential generation circuit is connected to the word line to supply the SRAM cells through the common connection line with a substrate potential determined by a selected or a non-selected state of the word line. The substrate potential is equal to a ground potential in the selected state or is put into a negative potential in the non-selected state. The substrate potential is given to each of drive transistors included in each SRAM to reduce a leak current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.