Wordline activation delay monitor using sample wordline located in data-storing array
US6115310A · kind A · utility
6Cited by
13References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1999 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Jan 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wordline activation delay monitor circuit is disclosed herein which includes a sample wordline located within a data-storing array of a memory, wherein the sample wordline is selected or activated by circuitry having substantially the same structure or location within the memory as circuitry which selects or activates wordlines of the data-storing array. A circuit is disclosed which determines a wordline activation delay for a first subarray group within the memory by activating a sample wordline which is located within a data-storing array of a second subarray group. Corresponding methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.