Integrated circuit using a power supply input for digital logic
US6115595A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | May 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01S19/32
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A GPS receiver including an RF GPS integrated circuit downconverter having a standby mode controlled by a power supply input used as a logic signal. The RF GPS integrated circuit includes a synthesizer for generating LO signals, first and second downconverters for using the LO signals for downconverting the GPS signal, and a sampler for using a clock signal for providing in-phase and quadrature phase sampled output signals representative of the GPS signal. The synthesizer includes a multi-mode divider for providing substantially the same first LO frequency at about the midpoint of the L1 and L2 GPS frequencies when either of an external or internally generated reference frequency is selected. A GPS digital signal processor integrated circuit issues the logic signal and the clock signal from a single pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.