Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and OFDM receiver and transmitter
US6115728A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Jan 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In fast Fourier transform, a necessary memory capacity is decreased, thereby decreasing a cost. The fast Fourier transform is performed on a symbol stored in a random access memory (RAM) by a butterfly operation unit in accordance with a RAM address generated by a RAM address generator. A RAM address conversion unit converts an input/output dummy address into an input/output real address by conducting bit reverse by a frequency specified in accordance with an input/output bit reverse signal, and converts a butterfly operation dummy address into a butterfly operation real address by conducting the bit reverse by a frequency specified in accordance with a butterfly operation bit reverse signal. In this manner, among output data of one symbol and input data of another symbol to be stored in the RAM subsequently to the output data of the one symbol, data having a common index indicating their orders in the symbols can be stored at the same address in the RAM. As a result, symbol input and symbol output can be overlapped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.