Method and apparatus for providing precise circuit delays
US6115769A · kind A · utility
5Cited by
49References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1996 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Jun 28, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.