Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions
US6115796A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1997 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Feb 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.