Non-aligned double word fetch buffer
US6115805A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1998 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Aug 7, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-aligned double word fetch buffer is integrated into a digital signal processor to handle non-aligned double word (32 bit) fetches. When a misaligned double word fetch is detected, the buffer causes a two cycle non-interruptable instruction to be initiated. The first cycle is a 16-bit misaligned data fetch. The address pointer is incremented by 2 and stored in a temporary pointer register. The second cycle is a 32-bit double word fetch based on the temporary pointer with its least significant bit set to 0 (an aligned fetch). The low word from this fetch is used to satisfy the current misaligned double word fetch and the high word is stored in a temporary buffer register in case it proves useful in subsequent misaligned double fetch instructions. Finally, the temporary address pointer is incremented by 2 for possible use in subsequent misaligned fetches. If a subsequent misaligned fetch using the same address pointer is detected, a one-cycle misaligned double word fetch may be simulated by using the buffered memory fetch data combined with another aligned double word fetch and an appropriate pointer update. A double word per cycle data rate may thereby be maintained during an e…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.