Memory paging scheme for 8051 class microcontrollers
US6115814A · kind A · utility
13Cited by
8References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1997 |
| Grant date | Sep 5, 2000 |
| Priority date | — |
| Expiry date | Nov 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A field-reprogammable storage control device has a microcontroller, a write-protected memory which contains a boot code for the storage control device, a rewriteable memory for application code executable by the microcontroller, and a jump function located in both the write-protected memory and the rewriteable memory for movement between the write-protected memory and the rewriteable memory for recover after a processing interruption. The storage control device remains operational using the write-protected memory and the boot code while receiving a new application code from a remote site.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.