Hardware-software co-synthesis of heterogeneous distributed embedded systems for low overhead fault tolerance
US6117180A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1998 |
| Grant date | Sep 12, 2000 |
| Priority date | — |
| Expiry date | Feb 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embedded systems employed in critical applications demand high reliability and availability in addition to high performance. Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, cost, reliability, and availability goals. The present invention addresses the problem of hardware-software co-synthesis of fault-tolerant real-time heterogeneous distributed embedded systems. Fault detection capability is imparted to the embedded system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. The reliability and availability of the architecture are evaluated during co-synthesis. On embodiment of the present invention, called COFTA, allows the user to specify multiple types of assertions for each task. It uses the assertion or combination of assertions that achieves the required fault coverage without incurring too much overhead. New methods are proposed to: 1) perform fault tolerance based task clustering, which determines the best placement of assertion and duplicate-and-compare tasks, 2) derive the best error recovery topology using a small n…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.