Method for increasing power supply bypassing while decreasing chip layer density variations

US6118169A · kind A · utility

Assignee

• AGILENT TECHNOLOGIES, INC. · US

Inventors

• Paul D Nuber · Fort Collins, US
• Dan Stotz · Fort Collins, US
• M. Jason Welch · Fort Collins, US
• Stephen E. Clarke · Carnduff, GB
• Guy Humphrey · Fort Collins, US
• C. Stephen Dondale · Fort Collins, US

Key dates

• Filing date: Dec 1, 1998
• Grant date: Sep 12, 2000
• Expiry date: Dec 1, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/90

Abstract

A method for increasing the layer density uniformity across a conductive layer, which comprises a plurality of functional blocks, of an integrated circuit is presented. Increased uniformity is achieved by tiling a plurality of capacitors in between the functional blocks. The configuration of the capacitor array and number of the capacitor cells in the array is arranged so as to provide approximate uniformity in the conductor-to-non-conductor density across the entire conductive layer. The capacitor array may be used to reduce power supply switching noise by coupling one or more of the capacitor cells making up the capacitor array between a high power rail and a low power rail.